The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Jul. 26, 2023
Applicant:
Nanya Technology Corporation, New Taipei City, TW;
Inventor:
Cheng-Hsiang Fan, Taoyuan City, TW;
Assignee:
NANYA TECHNOLOGY CORPORATION, New Taipei City, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); G11C 5/06 (2006.01); H10D 30/69 (2025.01); H10P 14/20 (2026.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01);
U.S. Cl.
CPC ...
H10D 30/797 (2025.01); G11C 5/063 (2013.01); H10D 30/021 (2025.01); H10P 14/2905 (2026.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01);
Abstract
The present disclosure provides a semiconductor memory structure, including a substrate, a gate structure, a first shallow trench isolation (STI), and a second STI. The gate structure, the first STI, and a second STI are disposed in the substrate. The gate structure is buried in the substrate. The gate structure is disposed between the first STI and the second STI.
Fan, Cheng-Hsiang. (2026). Semiconductor memory structure having drain stressor, source stressor and buried gate and method of manufacturing the same (U.S. Patent No. 12666659). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12666659
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile