The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
Jul. 25, 2023
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Kok Kiat Koo, Singapore, SG;
So Seetharam Gobalakrisnan, Singapore, SG;
Jürgen Schredl, Mering, DE;
Julian Treu, Munich, DE;
Dexter Inciong Reynoso, Singapore, SG;
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/04 (2026.01); H10W 70/40 (2026.01); H10W 70/60 (2026.01); H10W 72/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/047 (2026.01); H10W 70/421 (2026.01); H10W 70/611 (2026.01); H10W 90/00 (2026.01); H10W 72/073 (2026.01); H10W 72/884 (2026.01); H10W 90/734 (2026.01); H10W 90/753 (2026.01); H10W 90/756 (2026.01);
Abstract
A semiconductor device and method is disclosed. In one example, the semiconductor device includes a single first row of leads and a first chip carrier comprising a first electrically insulating layer arranged on the single first row of leads. At least one first semiconductor chip is mounted on the first electrically insulating layer, wherein the at least one first semiconductor chip is arranged over only the single first row of leads.