Memory device having an array of vertical transistors with associated lines and method for forming the same

Abstract

A three-dimensional memory device having vertical transistors and a method for forming the same are disclosed. In an example, the memory device includes an array of memory cells each including a vertical transistor. Along a first direction, one of the vertical transistors is arranged between two of separation structures in a plan view. Each of the separation structures includes a protrusion, and the separation structure and a corresponding protrusion are integral. The memory device also includes a plurality of bit lines that include at least one conductive layer. The at least one conductive layer is arranged between two protrusions of the two separation structures and on the one of vertical transistors to couple one of the bit lines with the one of the vertical transistors.