The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
May. 02, 2023
Applicant:
Neo Semiconductor, Inc., San Jose, CA (US);
Inventor:
Fu-Chang Hsu, San Jose, CA (US);
Assignee:
NEO Semiconductor, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10B 41/20 (2023.01); H10B 43/10 (2023.01); H10B 51/20 (2023.01); H10B 61/00 (2023.01); H10B 63/10 (2023.01); H10N 50/85 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/20 (2023.02); H10B 12/01 (2023.02); H10B 41/20 (2023.02); H10B 43/10 (2023.02); H10B 51/20 (2023.02); H10B 61/22 (2023.02); H10B 63/10 (2023.02); H10N 50/85 (2023.02); H10N 70/8828 (2023.02);
Abstract
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and insulating layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, and forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes.