The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Apr. 01, 2024
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Rupesh Singh, Ghaziabad, IN;

Ankur Bal, Greater Noida, IN;

Kirtiman Singh Rathore, Noida, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/02 (2006.01); H03K 3/037 (2006.01); H03K 5/1534 (2006.01); H03K 19/20 (2006.01); H03L 7/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/00 (2013.01); H03K 3/037 (2013.01); H03K 5/1534 (2013.01); H03K 19/20 (2013.01);
Abstract

A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.


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