Critical timing driven adaptive voltage frequency scaling

Abstract

An example method for critical timing driven adjustable voltage frequency scaling can include performing sensing operations on a system on chip (SoC) at a respective plurality of time windows each associated with a particular data value, comparing at least two of the particular data values associated with at least two respective time windows of the plurality of time windows, in response to the at least two of the particular data values being a same data value, determining that a clock margin is above a threshold clock margin, and determining that a clock margin is below a threshold clock margin. In some instance, in response to determining that the clock margin is above the threshold clock margin, a clocking of the SoC can be adjusted, a voltage of at least one operation of the SoC can be adjusted, and/or a clocking frequency of at least one operation of the SoC, among other possibilities.