The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Mar. 21, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Gokce Sarar, San Diego, CA (US);

Guillaume Shippee, La Jolla, CA (US);

Rhys Buggy, Enniskerry, IE;

Santanu Pattanayak, Bangalore, IN;

Tushit Jain, Bangalore, IN;

Suman Kumar Gunnala, San Diego, CA (US);

Kumar Raj, San Diego, CA (US);

Vatsal Nimeshkumar Thakkar, Longmont, CO (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/333 (2020.01); G06N 3/084 (2023.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); G06N 3/084 (2013.01);
Abstract

Certain aspects of the present disclosure provide techniques and apparatus for testing integrated circuit designs. An example method generally includes generating a coverage matrix associated with a plurality of test cases for an integrated circuit and coverage points associated with each test case of the plurality of test cases. A subset of the plurality of test cases is selected for execution based on weights associated with each test case of the plurality of test cases and a threshold weight value. Generally, the weights associated with each test case comprise weights in a machine learning model trained based on the coverage matrix. The integrated circuit may be tested based on the selected subset of test cases.


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