The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2026
Filed:
Mar. 15, 2022
On-chip digitally controlled error rate-locked loop for error resilient edge artificial intelligence
Intel Corporation, Santa Clara, CA (US);
Hechen Wang, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein relate to a neural network processor in a control loop, where the control loop sets an optimum supply voltage for the processor based on a measured error count or rate of the neural network. For example, if the measured error count is greater than a target level or range, the supply voltage can be increased. If the measured error count is below the target level or range, the supply voltage can be decreased. The error rate can be measured by providing an error detection circuit for one or more monitored nodes/processing units of a neural network. The error detection circuit can receive the same input data as the associated monitored processing unit, but operates on only a portion of the input data.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile