The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2026

Filed:

Feb. 20, 2023
Applicant:

Seriphy Technology Corporation, Hsinchu County, TW;

Inventors:

Tzu-Wei Chiu, Hsinchu County, TW;

Chun-Wei Chang, Taipei City, TW;

Shang-Pin Chen, Hsinchu County, TW;

Wei-Chih Chen, Taoyuan City, TW;

Che-Yen Huang, Hsinchu County, TW;

Assignee:

SERIPHY TECHNOLOGY CORPORATION, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10B 80/00 (2026.01); H10W 20/20 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10B 80/00 (2023.02); H10W 20/20 (2026.01); H10W 70/05 (2026.01); H10W 70/611 (2026.01); H10W 74/014 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/792 (2026.01); H10W 90/794 (2026.01);
Abstract

The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.


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