Scalable circuit-under-pad device topologies for lateral gan power transistors

Abstract

Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise source, drain and gate finger electrodes on active regions of a plurality of sections of a multi-section transistor, and a contact structure comprising source and drain contact areas, e.g. drain and source pads extending over active regions of each section, interconnected by conductive micro-vias to respective underlying drain and source finger electrodes. Alternatively, source contact areas comprise parts of a source bus which runs over inactive regions. For reduced gate loop inductance, the source bus may be routed over or under the to gate bus. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of the drain finger electrodes. Example CUP device structures provide for higher current carrying capability and reduced drain-source resistance.