The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2026

Filed:

Aug. 09, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Mariko Sumiya, Yokkaichi Mie, JP;

Ryosuke Yamamoto, Nagoya Aichi, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/35 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10P 14/20 (2026.01); H10P 90/00 (2026.01);
U.S. Cl.
CPC ...
H10B 43/35 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10P 14/2905 (2026.01); H10P 90/1914 (2026.01);
Abstract

A method for manufacturing a semiconductor device includes: forming a release layer including a first polycrystalline semiconductor layer provided on a first substrate, and a second polycrystalline semiconductor layer provided between the first substrate and the first polycrystalline semiconductor layer and having a p-type impurity concentration which is lower than that of the first polycrystalline semiconductor layer, and an n-type impurity concentration which is higher than that of the first polycrystalline semiconductor layer; subjecting the first polycrystalline semiconductor layer to anodic chemical conversion to form a first porous layer; forming a first device layer on the first porous layer; and bonding together the first device layer and a second device layer provided on a second substrate.


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