Hybrid timing windows in clock tree synthesis

Abstract

A hybrid window scheme for defining timing windows during CTS. CTS is performed to generate an intermediate clock tree including a respective insertion delay for each of the one of more flip-flops. A set of clock timing constraints is generated for the plurality of slack values of each flip-flop such that every positive slack value of the plurality of slack values is prevented from becoming negative, a lowest negative slack value of the one or more negative slack values is prevented from becoming lower, and every negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value is prevented from becoming lower than the lowest negative slack value but is allowed to become lower than its current value. A second iteration of CTS is performed, constrained by the clock timing constraints, resulting in an enhanced clock tree.