The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

May. 16, 2023
Applicant:

Asml Netherlands B.v., Veldhoven, NL;

Assignee:

ASML Netherlands B.V., Veldhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 46/00 (2026.01); G06F 21/44 (2013.01); G06F 21/73 (2013.01); G06K 7/14 (2006.01); G06K 19/06 (2006.01); G09C 5/00 (2006.01); H04L 9/14 (2006.01); H04L 9/32 (2006.01); H04L 9/40 (2022.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 46/00 (2026.01); G06F 21/44 (2013.01); G06F 21/73 (2013.01); G06K 7/1417 (2013.01); G06K 19/06037 (2013.01); G06K 19/06178 (2013.01); G09C 5/00 (2013.01); H04L 9/14 (2013.01); H04L 9/3271 (2013.01); H04L 63/08 (2013.01); H10W 90/00 (2026.01); G06F 2221/2103 (2013.01); H10W 46/106 (2026.01); H10W 46/401 (2026.01); H10W 46/403 (2026.01);
Abstract

A method includes generating pattern data including common chip design data and one or more bit spaces or place holders reserved for non-common chip design data or information related to the non-common chip design data. The method includes introducing the non-common chip design data or information related to the non-common chip design data into the one or more bit spaces or place holders of the pattern data before streaming the pattern data to the maskless pattern writer. The common chip design data defines a common design layout part of an electronic device to be created on a wafer using the maskless pattern writer. The non-common chip design data defines a non-common design layout part of the electronic device to be created on the wafer using the maskless pattern writer, the non-common design layout part being different from other electronic devices created on the wafer.


Find Patent Forward Citations

De Langen, Johannes Cornelis Jacobus. (2026). Method and systems for creating electronic devices via maskless lithography (U.S. Patent No. 12648451). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12648451

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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