The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Dec. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Burak Baylav, Hillsboro, OR (US);

Nidhi Khandelwal, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 89/10 (2025.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
H10D 89/10 (2025.01); G06F 30/392 (2020.01);
Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to filling in whitespace between one or more groups of functional circuits on a wafer. The whitespace may be divided into a plurality of cells including periphery cells and central cells, where a portion of the cells may have the same design, where a characteristic of the plurality of cells, for example a density of metal within the cell, may be designed in order to facilitate the fabrication process of the wafer. Other embodiments may be described and/or claimed.


Find Patent Forward Citations

Baylav, Burak. (2026). Transition cells between design blocks on a wafer (U.S. Patent No. 12648229). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12648229

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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