The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Oct. 31, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyumin Yoo, Suwon-si, KR;

Myung Gil Kang, Suwon-si, KR;

Dongwon Kim, Suwon-si, KR;

Jongsu Kim, Suwon-si, KR;

Beomjin Park, Suwon-si, KR;

Byeonghee Son, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/13 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 62/149 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 62/116 (2025.01);
Abstract

A semiconductor device includes a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are stacked to be spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a blocking layer between the source/drain pattern and the active pattern, wherein the source/drain pattern includes a protruding side surface protruding toward the semiconductor patterns, the blocking layer includes silicon-germanium (SiGe), and a germanium concentration of the blocking layer is higher than a germanium concentration of the source/drain pattern.


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