The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2026
Filed:
Jul. 14, 2022
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Anhao Cheng, Taichung City, TW;
Ching-Hung Kao, Tainan City, TW;
Yen-Liang Lin, Tainan City, TW;
Meng-I Kang, Changhua County, TW;
Kai-Chi Wu, Changhua County, TW;
Chien-Wei Lee, Taichung City, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A semiconductor structure including a substrate, a first well region, a second well region, an isolation, a gate structure, and a dielectric layer is provided. The first well region is disposed in the substrate, wherein a dopant of the first well region includes arsenic. The second well region is disposed in the substrate under the first well region, wherein the second well region has a conductivity type different from that of the first doping region. The isolation is disposed in the substrate and surrounds the first well region, wherein a depth of the isolation is substantially greater than or equal to a depth of the first well region from a first surface of the substrate. The gate structure are disposed sequentially over the substrate and overlaps the first well region. A method of forming the semiconductor structure is also provided.