The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2026
Filed:
Jun. 21, 2024
Cadence Design Systems, Inc., San Jose, CA (US);
Hajee Mohammed Shuaeb Fazeel, Bengaluru, IN;
Vinod Kumar, Uttar Pradesh, IN;
Thomas Evan Wilson, Laurel, MD (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Embodiments included herein are directed towards a sampler circuit. Embodiments may include a first positive-channel metal oxide semiconductor (PMOS) or negative-channel metal oxide semiconductor (NMOS) transistor that may be operatively connected to a voltage source and a first output node. A cross-coupled PMOS/NMOS pair may be operatively connected to the first PMOS/NMOS transistor, respectively, and a pair of first stage output nodes may be operatively connected to the cross-coupled PMOS/NMOS pair, respectively, where the pair of first stage output nodes may include a positive node and a negative node. An input differential pair may be operatively connected to the pair of first stage output nodes, and an offset current digital-to-analog converter (DAC) may be operatively connected to a first side of the input differential pair, while an offset current DAC replica may be operatively connected to a second side of the input differential pair.