The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2026
Filed:
Jan. 09, 2023
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Frederick A. Ware, Los Altos Hills, CA (US);
Ely Tsern, Los Altos, CA (US);
John Eric Linstadt, Palo Alto, CA (US);
Assignee:
Rambus Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/005 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/1004 (2013.01); G06F 11/1076 (2013.01); G11C 5/04 (2013.01); G11C 5/063 (2013.01); G11C 7/1057 (2013.01); G11C 7/1078 (2013.01); G11C 7/12 (2013.01);
Abstract
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.