The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Aug. 27, 2024
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Santhosh Reddy Akavaram, Hyderabad, IN;

Sang Tran, Encinitas, CA (US);

Vydhik Sharma Devaraju, Karimnagar, IN;

Chintalapati Bharath Sai Varma, Hyderabad, IN;

Radhakrishna Mugada, Hyderabad, IN;

Pradeep Cherukoori, Wyra, IN;

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/64 (2013.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 13/4068 (2013.01);
Abstract

Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.


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