The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2026
Filed:
Mar. 27, 2020
Intel Corporation, Santa Clara, CA (US);
Eran Shifer, Tel Aviv, IL;
Zeshan A. Chishti, Hillsboro, OR (US);
Sanjay K. Kumar, Hillsboro, OR (US);
Zvika Greenfield, Kfar Sava, IL;
Philip Lantz, Cornelius, OR (US);
Eshel Serlin, Hod Hasharon, IL;
Asaf Rubinstein, Kefar Sava, IL;
Robert J. Royer, Jr., Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.