The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2026
Filed:
Jun. 27, 2023
Applicant:
Mediatek Inc., Hsinchu City, TW;
Inventors:
Assignee:
MEDIATEK INC., Hsinchu City, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 23/3157 (2013.01); H01L 23/3107 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/182 (2013.01);
Abstract
A semiconductor package structure includes a substrate, a dummy conductive mesh structure, an interposer, an underfill material, and a semiconductor die. The substrate includes a wiring structure in dielectric layers. The dummy conductive mesh structure is embedded in the substrate and is spaced apart from the wiring structure by the dielectric layers. The interposer is disposed over the substrate. The underfill material extends between the substrate and the interposer and over the dummy conductive mesh structure. The semiconductor die is disposed over the interposer and is electrically coupled to the wiring structure through the interposer.