Semiconductor package and method of fabricating the same

Abstract

A semiconductor package including a substrate comprising a plurality of vias; a chip stack on the substrate; and a mold layer on the substrate and on at least a portion of the chip stack. The chip stack includes a first semiconductor chip; second semiconductor chips stacked on the first semiconductor chip; a third semiconductor chip on the uppermost one of the second semiconductor chips; and non-conductive layers between the first semiconductor chip and the second semiconductor chips. A first chip pad of the first semiconductor chip is bonded to a substrate pad of the substrate. A second chip pad of the uppermost one of the second semiconductor chips is bonded to a third chip pad of the third semiconductor chip. Each of the second semiconductor chips is electrically connected to another of the second semiconductor chips or the first semiconductor chip.