The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Aug. 08, 2023
Applicant:

Monolithic Power Systems, Inc., Kirkland, WA (US);

Inventors:

Vipindas Pala, San Jose, CA (US);

Sauvik Chowdhury, San Jose, CA (US);

Assignee:

Monolithic Power Systems, Inc., Kirkland, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/66 (2025.01); H10D 30/83 (2025.01); H10D 62/10 (2025.01); H10D 84/00 (2025.01);
U.S. Cl.
CPC ...
H10D 84/141 (2025.01); H10D 30/0291 (2025.01); H10D 30/0297 (2025.01); H10D 30/0512 (2025.01); H10D 30/615 (2025.01); H10D 30/668 (2025.01); H10D 30/83 (2025.01); H10D 30/831 (2025.01); H10D 62/107 (2025.01); H10D 62/127 (2025.01);
Abstract

A method for manufacturing a semiconductor device includes preparing a substrate of a first conductivity type having a drain region, forming a first source region and a second source region of the first conductivity type in the substrate separated from each other, and forming a gate trench of a gate region disposed closely next to or in adjoining neighbor to the first source region. The method may further include forming a first sidewall body region of a second conductivity type to separate the first source region from the second source region, forming a link region of the second conductivity type such that the link region and the gate trench are disposed spatially opposite to each other, forming a gate insulation layer to coat and line sidewalls and a bottom of the gate trench, and using a gate conductive material to fill the gate trench.


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