The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2026
Filed:
Dec. 02, 2024
Cadence Design Systems, Inc., San Jose, CA (US);
Mark A. Summers, Cary, NC (US);
Kelvin E. Mccollough, Garner, NC (US);
Douglas Scott Shelton, Kingsville, MD (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Various example embodiments provide for handling phase interpolator (PI) integral non-linearity (INL) errors based on phase error measurements, which can be used in conjunction with clock data recovery (CDR) within a circuit, such as a data serializer/deserializer (SerDes) circuit. In particular, various example embodiments provide a PI system configured to measure and handle (e.g., reduce or correct) PI integral INL errors, where the PI system comprises a PI, a phase detector, a first-order path, a second-order loop, a phase integrator, a measurement component, and a look-up-table (LUT) component. For various example embodiments, the measurement component is configured to receive phase error information for an input data signal from the phase detector, receive frequency offset information from the second-order loop, receive phase position data for the input signal to the PI, and adjust mappings of one or more phase positions to the PI to reduce or correct non-linearity in the PI.