The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2026
Filed:
Mar. 13, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Tsmc Nanjing Company, Limited, Nanjing, CN;
Yi Yun Huang, Hsinchu, TW;
Feng Lin, Hsinchu, TW;
Siliang Xie, Hsinchu, TW;
Pingping Liu, Hsinchu, TW;
Qingchao Meng, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
TSMC NANJING COMPANY, LIMITED, Nanjing, CN;
Abstract
A delay-enhanced inverter circuit (DE-inverter) includes: a non-delay-enhanced inverter circuit (NE-inverter) having an output at a first node and an input at a second node; and a capacitive device feedback-coupled between the first node and the second node. The capacitive device includes: a first positive-channel metal-oxide (PMOS) field-effect transistor (FET) (PFET) feedback-coupled between the first node and the second node, the first PFET having a capacitor-configuration; and a first negative-channel metal-oxide (NMOS) FET (NFET) feedback-coupled between the first node and the first reference voltage, the first NFET having a capacitor-configuration.