The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Dec. 08, 2021
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Srinivas Satish Babu Bamdhamravuri, Newbury Park, CA (US);

Panduka Wijetunga, Thousand Oaks, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 8/18 (2006.01); G11C 11/4063 (2006.01); G11C 29/50 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50012 (2013.01); G11C 7/222 (2013.01); G11C 8/18 (2013.01); G11C 11/4063 (2013.01); G11C 29/56004 (2013.01); G11C 29/56012 (2013.01); G11C 2029/5602 (2013.01);
Abstract

Technologies for signal skew correction in integrated circuit memory devices are described. An integrated circuit memory device includes a first interface to receive command/address (CA) signals and a clock signal, a data interface, and a mode register. During a CA bus loopback mode, the first interface receives a pattern of CA signals and the clock signal and the data interface outputs the pattern of CA signals. During the CA bus loopback mode, the mode register can be programmed with a value representative of a timing offset between the clock signal and a sampling point for the first interface.


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