The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2026
Filed:
Jul. 10, 2024
Micron Technology, Inc., Boise, ID (US);
Shyam Sunder Raghunathan, Woodlands, SG;
Yingda Dong, Los Altos, CA (US);
Akira Goda, Tokyo, JP;
Leo Raimondo, Avezzano, IT;
Micron Technology, Inc., Boise, ID (US);
Abstract
Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.