The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2026
Filed:
Apr. 02, 2024
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Tsmc Nanjing Company, Limited, Nanjing, CN;
Chia-Cheng Chen, Hsinchu, TW;
Jun Xie, Hisnchu, TW;
Ching-Wei Wu, Hsinchu, TW;
Luping Kong, Hsinchu, TW;
Chien-Yu Huang, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
TSMC NANJING COMPANY, LIMITED, Nanjing, CN;
Abstract
A memory circuit includes a first and second inverter, and a level shifter circuit. The first inverter is coupled to a first voltage supply, and configured to generate a first input signal in response to a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured generate a first and second signal responsive to a first or second input signal. The second inverter is configured to generate a word line signal in response to the first signal. The level shifter circuit is configured to delay a leading edge of the word line signal in response to the first or second signal. An amount of delay of the leading edge of the word line signal is based on a voltage difference between the first and second supply voltage. The first supply voltage has a first swing. The second supply voltage has a second swing.