Memory device and system, and decoding circuit

Abstract

The present disclosure provides a memory device and system, and a decoding circuit. The memory device includes a memory cell array and a peripheral circuit coupled with the memory cell array; the memory cell array includes at least one block, and the block is provided with multiple rows of word lines, multiple columns of bit lines, and memory cells coupled between the word lines and the bit lines; the peripheral circuit includes a column decoding circuit; the column decoding circuit is coupled with the multiple columns of bit lines and configured to receive a column address signal, perform multi-stage decoding on the column address signal, and output a column select signal indicative of enabling a respective bit line in the block.