The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Apr. 22, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Xiaoyu Sun, Hsinchu City, TW;

Brian Crafton, Hsinchu City, TW;

Murat Kerem Akarvardar, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1057 (2013.01); G11C 7/1012 (2013.01); G11C 7/1096 (2013.01);
Abstract

A memory circuit includes an array, a first buffer, a second buffer, a fetch circuit, and a controller. The fetch circuit can be configured to fetch a first subset of a first data elements from the first buffer and temporarily store the first subset of the first data elements, during a first cycle to write the first subset of the first data elements to a first subset of a plurality of processing elements (PEs) arranged along a first one of rows in the array. The controller can be configured to control the fetch circuit to selectively limit fetching a second subset of the first data elements from the first buffer, during a second subsequent cycle to write a second subset of the first data elements to a second subset of the PEs arranged along a second one of the rows.


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Sun, Xiaoyu. (2026). System and method for improving efficiency of multi-storage-row compute-in-memory (U.S. Patent No. 12640174). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12640174

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