The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Sep. 27, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aneesh Aggarwal, Portland, OR (US);

Georgii Tkachuk, Phoenix, AZ (US);

Subhiksha Ravisundar, Gilbert, AZ (US);

Youngsoo Choi, Alameda, CA (US);

Niall Mcdonnell, Limerick, IE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/06 (2006.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0897 (2013.01); G06F 12/063 (2013.01);
Abstract

An example of an apparatus may include a first cache organized as two or more portions, a second cache, and circuitry coupled to the first cache and the second cache to determine a designated portion allocation for data transferred from the first cache to the second cache, and track the designated portion allocation for the data transferred from the first cache to the second cache. Other examples are disclosed and claimed.


Find Patent Forward Citations

Aggarwal, Aneesh. (2026). Multi-level cache data tracking and isolation (U.S. Patent No. 12639231). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12639231

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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