The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Apr. 17, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kirill Kazatsker, Ramat Gan, IL;

Keren Guy, Sunnyvale, CA (US);

Anjali Singhai Jain, Portland, OR (US);

Matthew Vick, Hillsboro, OR (US);

Jayaprakash Shanmugam, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 8/65 (2018.01); G06F 3/06 (2006.01); G06F 21/51 (2013.01); G06F 21/57 (2013.01); H04L 41/0806 (2022.01); H04L 41/0816 (2022.01); H04L 41/0895 (2022.01); H04L 67/00 (2022.01); H04L 41/046 (2022.01); H04L 41/082 (2022.01); H04L 41/14 (2022.01); H04L 41/16 (2022.01);
U.S. Cl.
CPC ...
G06F 8/65 (2013.01); G06F 3/0604 (2013.01); G06F 3/0607 (2013.01); G06F 3/0632 (2013.01); G06F 3/0679 (2013.01); G06F 21/51 (2013.01); G06F 21/57 (2013.01); H04L 41/0806 (2013.01); H04L 41/0816 (2013.01); H04L 41/0895 (2022.05); H04L 67/34 (2013.01); H04L 41/046 (2013.01); H04L 41/082 (2013.01); H04L 41/145 (2013.01); H04L 41/16 (2013.01);
Abstract

Examples described herein relate to a network interface device. In some examples, the network interface device includes a network interface device that includes a network interface, a host interface, and multiple processors. In some examples, a first processor of the multiple processors is to execute a first control plane process and an embedded software update is to occur by: installation and execution of a second control plane process on the first processor and a third control plane process is to cause utilization of the second control plane process.


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