The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2026

Filed:

Jul. 30, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Juane Li, San Jose, CA (US);

Fanqi Wu, Sunnyvale, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 3/06 (2006.01); G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 29/00 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0613 (2013.01); G06F 3/0647 (2013.01); G06F 3/0679 (2013.01); G06F 11/102 (2013.01); G11C 29/44 (2013.01);
Abstract

Various aspects of the present disclosure relate to determining data migration priorities in a memory sub-system. A processing device performs a scan operation, such as a read disturb scan, to detect one or more errors in a memory block of the plurality of memory blocks. The processing device determines, based on a result of the scan operation, to perform a data migration operation to move data from one or more memory segments of the memory device to one or more other memory segments of the memory device, wherein the one or more memory segments of the memory device include at least one page of the memory block. The processing logic determines a corresponding priority level of the data migration operation. The processing logic performs the data migration operation based on the corresponding priority level.


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