The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jul. 21, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyungjoo Na, Suwon-si, KR;

Woo Bin Song, Suwon-si, KR;

Jin-Wook Yang, Suwon-si, KR;

Cheoljin Yun, Suwon-si, KR;

Yoshinao Harada, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/23 (2025.01); H01L 23/48 (2006.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/66 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 64/258 (2025.01); H01L 23/481 (2013.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/665 (2025.01); H10D 64/668 (2025.01); H10D 84/85 (2025.01);
Abstract

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns that are spaced apart from each other and are vertically stacked, a source/drain pattern connected to the plurality of semiconductor patterns, a through pattern penetrating the source/drain pattern, a metal-semiconductor compound layer between the source/drain pattern and the through pattern, a gate electrode on the plurality of semiconductor patterns, the gate electrode including inner electrodes between adjacent semiconductor patterns of the plurality of semiconductor patterns and an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns, an active contact on the through pattern, and a first metal layer on the active contact, the first metal layer including a power wiring and first wirings connected to the active contact.


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