The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jun. 01, 2023
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Boon Keat Toh, Singapore, SG;

Chih-Hsin Chang, Hsinchu County, TW;

Szu Han Wu, Hsinchu City, TW;

Chi Ren, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/68 (2025.01); H10B 41/35 (2023.01); H10D 30/01 (2025.01); H10D 62/83 (2025.01); H10D 64/62 (2025.01);
U.S. Cl.
CPC ...
H10D 30/68 (2025.01); H10B 41/35 (2023.02); H10D 30/022 (2025.01); H10D 30/0411 (2025.01); H10D 62/83 (2025.01); H10D 64/62 (2025.01);
Abstract

Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate having a first memory region. The first memory region includes a first dielectric layer, a first floating gate, a first inter-gate dielectric layer, a control gate and a first contact. The first dielectric layer is disposed on the substrate. The first floating gate is disposed on the first dielectric layer. The first inter-gate dielectric layer is disposed on the first floating layer. The control gate is disposed on the first inter-gate dielectric layer. The first contact penetrates through the first control gate and the first inter-gate dielectric layer and is landed on the first floating gate.


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