The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jun. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Li-Zhen Yu, New Taipei City, TW;

Lin-Yu Huang, Hsinchu, TW;

Huan-Chieh Su, Tianzhong Township, Changhua County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/43 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/62 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6713 (2025.01); H01L 21/02603 (2013.01); H01L 21/28123 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/62 (2025.01); H10D 64/679 (2025.01);
Abstract

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures over a substrate, and a gate structure surrounding the nanostructures. The gate structure includes gate dielectric layers and gate electrode layers. The semiconductor structure also includes a source/drain (S/D) structure adjacent to the gate structure, and an inner spacer layer between the gate structure and the S/D structure. The semiconductor structure further includes a filling layer over the gate structure, and the filling layer has a protrusion portion embedded in a space, the space is surrounded by the inner spacer, the gate dielectric layer and the gate electrode layer. The semiconductor structure also includes a first S/D contact structure formed over the filling layer.


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