The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Mar. 23, 2023
Applicant:

SK Keyfoundry Inc., Cheongju-si, KR;

Inventors:

Jong Yeul Jeong, Cheongju-si, KR;

Sang Geun Koo, Cheongju-si, KR;

Jeong Ho Sheen, Cheongju-si, KR;

Kang Sup Shin, Cheongju-si, KR;

Assignee:

SK keyfoundry Inc., Cheongju-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/00 (2025.01); H10D 1/68 (2025.01); H10D 84/00 (2025.01);
U.S. Cl.
CPC ...
H10D 1/042 (2025.01); H10D 1/716 (2025.01); H10D 84/212 (2025.01);
Abstract

A method for manufacturing a semiconductor device includes providing a high-voltage isolation capacitor region on a substrate, forming a bottom electrode in the high-voltage isolation capacitor region, forming an inter-metal dielectric layer on the bottom electrode, forming a low bandgap dielectric layer on the inter-metal dielectric layer, forming a first hard mask layer on the low bandgap dielectric layer, patterning the first hard mask layer and the low bandgap dielectric layer to form a patterned first hard mask layer and a patterned low bandgap dielectric layer, depositing a thick metal film on the patterned first hard mask layer and the patterned low bandgap dielectric layer, and patterning the thick metal film to form a top electrode in the high-voltage isolation capacitor region, such that the top electrode overlaps the patterned first hard mask layer and the patterned low bandgap dielectric layer.


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