Semiconductor die stacks and associated systems and methods

Abstract

Semiconductor die stacks and associated systems and methods are disclosed. In an embodiment, a semiconductor die stack corresponds to a pair of a logic die and a memory die directly bonded together. The logic die includes integrated circuits generated by relatively high temperature process steps whereas the memory die includes memory cells with materials generated using relatively low temperature process steps. A logic wafer including the logic dies and a memory wafer including the memory dies are separately fabricated. Subsequently, the logic wafer and the memory wafer are directly bonded to generate the semiconductor die stacks. Either the logic dies or the memory dies include through-substrate vias (TSVs) to provide power and signals for the semiconductor die stacks. The resulting semiconductor devices operate as a single device as if they were formed in a monolithic substrate.