The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Dec. 29, 2022
Applicant:

Kepler Computing Inc., San Francisco, CA (US);

Inventors:

Debraj Guhabiswas, Berkeley, CA (US);

Alexis Corda, Union City, CA (US);

Maria Isabel Perez, Berkeley, CA (US);

Jason Y. Wu, Albany, CA (US);

Neil Quinn Murray, Albany, CA (US);

Somilkumar J. Rathi, San Jose, CA (US);

Niloy Mukherjee, San Ramon, CA (US);

Rajeev Kumar Dokania, Beaverton, OR (US);

Amrita Mathuriya, Portland, OR (US);

Sasikanth Manipatruni, Portland, OR (US);

Assignee:

Kepler Computing Inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 53/30 (2023.01); G11C 11/22 (2006.01); H01L 21/02 (2006.01); H10D 1/68 (2025.01);
U.S. Cl.
CPC ...
H10B 53/30 (2023.02); G11C 11/221 (2013.01); H01L 21/02197 (2013.01); H10D 1/688 (2025.01);
Abstract

A method of fabricating a device comprising forming a multi-layer stack by sequentially depositing a first conductive layer, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, a third conductive layer comprising one or more of ruthenium, platinum, or iridium on the second conductive layer, and depositing an insulator layer on the third conductive layer. The method further comprises patterning the multi-layer stack to form a device by utilizing a plasma etch process.


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