The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Sep. 06, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Sidhartha Gupta, Boise, ID (US);

Matthew J. King, Boise, ID (US);

Jiewei Chen, Meridian, ID (US);

Yi Hu, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/02 (2006.01); H10B 41/27 (2023.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01); H10B 43/50 (2023.01);
U.S. Cl.
CPC ...
H10B 43/50 (2023.02); H10B 41/27 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02);
Abstract

An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures adjacent to a source, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprising a channel material extending vertically through the stack. The electronic device comprises an additional stack adjacent to the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, pillars extending through the additional stack and adjacent to the strings of memory cells, conductive contacts adjacent to the pillars, and isolation structures laterally intervening between neighboring pillars. The isolation structures exhibit a weave pattern, and portions of the isolation structures are laterally adjacent to and physically contact the conductive contacts. Related memory devices, systems, and methods are also described.


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