The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jan. 08, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Han Lin, Hsinchu, TW;

Chih-Ren Hsieh, Changhua, TW;

Chen-Chin Liu, Hsinchu, TW;

Chih-Pin Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/50 (2023.01); H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 21/321 (2006.01); H10B 41/10 (2023.01); H10B 41/41 (2023.01); H10D 30/68 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01);
U.S. Cl.
CPC ...
H10B 41/50 (2023.02); H01L 21/0337 (2013.01); H01L 21/3086 (2013.01); H01L 21/3212 (2013.01); H10B 41/10 (2023.02); H10B 41/41 (2023.02); H10D 30/6892 (2025.01); H10D 64/037 (2025.01); H10D 64/693 (2025.01); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02);
Abstract

Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.


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