The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2026
Filed:
Dec. 17, 2024
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Pavan Kumar Kasibhatla, Bengaluru, IN;
Jitendra Mishra, Bangalore, IN;
Assignee:
Rambus Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03L 7/081 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0025 (2013.01); H03L 7/0814 (2013.01); H04L 7/033 (2013.01);
Abstract
A timing-calibration circuit uses an active phase interpolator to calibrate clock delays through a number of passive fractional delay elements. The timing-calibration circuit minimizes system-wide power consumption by limiting the number and usage of active phase interpolators for delay adjustment in favor of the passive fractional delay elements.
Kasibhatla, Pavan. (2026). Power efficient circuits and methods for phase alignment (U.S. Patent No. 12634105). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12634105
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile