The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jul. 30, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chao-I Wu, Hsinchu, TW;

Shih-Lien Linus Lu, Hsinchu, TW;

Sai-Hooi Yeong, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); G06F 11/20 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G06F 11/2094 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01);
Abstract

A method of testing a three dimensional (3D) memory cell array includes applying a first voltage to word lines of each layer of memory cells in the 3D memory cell array thereby performing a write operation of the 3D memory cell array, simultaneously performing a read operation of each memory cell in a first layer of the 3D memory cell array, determining that each memory cell in the first layer has not failed in response to the read operation, and not replacing at least one failed memory cell in the first layer with a first spare memory cell. The simultaneously performing the read operation of each memory cell in the first layer includes comparing a first total read current of each memory cell in the first layer with a first expected read current of each memory cell in the first layer.


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