All levels program operation integrated with corrective program verify operation in a memory device

Abstract

A memory device including a memory array including a set of target memory cells connected to a target wordline; and a first wordline adjacent to the target wordline, wherein the first wordline is to be programmed immediately subsequent to the target wordline; and control logic, operatively coupled with the memory array, to perform operations including causing, during a first time period of a program operation, a ramping wordline voltage to be applied to the set of target memory cells of the target wordline; causing, during the first time period, a disconnection of a set of pillars associated with the set of memory cells from a voltage supply and ground voltage, wherein each pillar corresponds to a respective programming level of a set of programming levels; causing, during a second time period of the program operation, a programming pulse to be applied to the set of target memory cells, wherein the programming pulse programs each programming level of the set of programming levels associated with the set of target memory cells; identify, based on programming level information of the first wordline, a program verify (PV) voltage offset associated with the target wordline; and causing, during a program verify time period of the program operation, a program verify voltage to be applied to the target wordline to verify programming of the set of target memory cells to a target programming level, wherein the program verify voltage is adjusted by the PV voltage offset.