The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Apr. 02, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shreesha Srinath, Portland, OR (US);

Jonathan Pearce, Portland, OR (US);

David B. Sheffield, Portland, OR (US);

Ching-Kai Liang, Beaverton, OR (US);

Jeffrey Cook, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3016 (2013.01); G06F 9/30065 (2013.01); G06F 9/30087 (2013.01); G06F 9/3009 (2013.01); G06F 9/522 (2013.01);
Abstract

Techniques for using soft-barrier hints are described. An example includes a synchronous microthreading (SyMT) co-processor coupled to a logical processor to execute a plurality of microthreads, with each microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode, wherein the SyMT co-processor is further to support a soft-barrier hint instruction in code which when processed by a microthread is to pause execution of the microthread to be resumed based at least in part on a data structure having at least one entry, the entry to include an instruction pointer of the soft-barrier hint instruction and a count of microthreads that have encountered the soft-barrier hint instruction at the instruction pointer.


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