The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2026
Filed:
Jun. 20, 2024
Globalfoundries U.s. Inc., Malta, NY (US);
Nithin Thomas Abraham, Bangalore, IN;
Balaji Sahebrao Rathod, Bangalore, IN;
Asif Iqbal, Bangalore, IN;
GlobalFoundries U.S. Inc., Malta, NY (US);
Abstract
Disclosed are a structure and method for generating a reference voltage (VREF) that remains essentially constant in response variations in temperature and/or variations in a positive supply voltage. The structure can include a VREF generation circuit with a first stage for generating a first complementary-to-absolute temperature voltage (V_CTAT), a second stage for generating a second complementary-to-absolute temperature voltage (V_CTAT) higher than but exhibiting the same temperature-dependent rate of change as V_CTAT, and an output stage for generating VREF as a function of the difference between V_CTATand V_CTAT(e.g., VREF can be approximately equal to V_CTATminus V_CTAT). In this structure, the same bias voltage (VBIAS) is employed for each stage and all transistors can be metal oxide semiconductor field effect transistors (MOSFETs). With the disclosed configuration, a more stable VREF across a wider temperature range and/or VDD range is achievable and the structure may consume less chip area.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile