The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2026

Filed:

Jun. 15, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wei Lee, Hsinchu City, TW;

Katherine H Chiang, New Taipei City, TW;

Pei-Wen Liu, Hsinchu City, TW;

Ke-Wei Su, Hsinchu County, TW;

Kuan-Lun Cheng, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N 27/414 (2006.01); B01L 3/00 (2006.01);
U.S. Cl.
CPC ...
G01N 27/4145 (2013.01); B01L 3/502715 (2013.01); G01N 27/4148 (2013.01); B01L 2200/16 (2013.01); B01L 2300/0636 (2013.01); B01L 2300/0645 (2013.01); B01L 2300/1827 (2013.01);
Abstract

A semiconductor structure includes an isolation structure penetrating through a semiconductor substrate, a biosensor coupled to the semiconductor substrate, and a cover. The biosensor includes a bio-sensing device, a voltage-reference device spaced apart from the bio-sensing device, thermal management devices in proximity to the bio-sensing device, and a patterned dielectric layer. Each of the bio-sensing and voltage-reference devices includes a gate structure disposed on a bottom surface of the semiconductor substrate, source/drain (S/D) regions disposed in the semiconductor substrate, and a portion of a sensing film disposed on the semiconductor substrate and capacitively coupled to the gate structure and the S/D regions. Each thermal management devices includes a gate structure underlying the isolation structure or the semiconductor substrate. The patterned dielectric layer overlying the semiconductor substrate includes sensing wells located above the voltage-reference and bio-sensing devices. The cover overlying the patterned dielectric layer includes fluid channels communicating with the sensing wells.


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