The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2026
Filed:
Dec. 23, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Ronald Spreitzer, Phoenix, AZ (US);
Jason Garcia, Scottsdale, AZ (US);
Ankur Agrawal, Chandler, AZ (US);
Eleanor Patricia Paras Rabadam, Folsom, CA (US);
Guiyun Bai, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01S 5/0234 (2021.01); H01S 5/50 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3157 (2013.01); B81B 7/007 (2013.01); B81C 1/00301 (2013.01); H01L 21/4853 (2013.01); H01L 21/563 (2013.01); H01L 24/16 (2013.01); B81B 2207/07 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/146 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/18161 (2013.01); H01S 5/0234 (2021.01); H01S 5/50 (2013.01);
Abstract
Example techniques to enable a flip chip underfill exclusion zone include use of bump barriers, films or etched substrate cavities to prevent underfill from reaching the flip chip underfill exclusion zone.
Spreitzer, Ronald. (2026). Techniques to enable a flip chip underfill exclusion zone (U.S. Patent No. 12628686). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12628686
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile