The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Dec. 05, 2023
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Junjie Li, Beijing, CN;

Enxu Liu, Beijing, CN;

Na Zhou, Beijing, CN;

Jianfeng Gao, Beijing, CN;

Junfeng Li, Beijing, CN;

Jun Luo, Beijing, CN;

Wenwu Wang, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/13 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 62/151 (2025.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01);
Abstract

A method for manufacturing a semiconductor and a semiconductor. The method includes: providing a substrate, wherein an active region trench is on the substrate, and a channel stack of a gate-all-around transistor is formed in the active region trench, the active region trench is divided into a source trench and a drain trench by the channel stack; epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench, and stopping epitaxial growth before crystal planes with different orientations of the source crystal structure intersect and crystal planes with different orientations of the drain crystal structure intersect; and filling gaps between the crystal planes with different orientations of the source crystal structure and the drain crystal structure by using an isotropic metal material, and forming a source and a drain of the gate-all-around transistor in the source trench and the drain trench, respectively.


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