The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2026

Filed:

Feb. 03, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu City, TW;

Inventors:

Chih-Wei Yang, Tainan City, TW;

Ssu-I Fu, Kaohsiung City, TW;

Chih-Kai Hsu, Tainan City, TW;

Chun-Hsien Lin, Tainan City, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H01L 21/02 (2006.01); H10D 30/62 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0243 (2025.01); H01L 21/02293 (2013.01); H10D 30/62 (2025.01); H10D 64/311 (2025.01);
Abstract

A method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first gate structure on the substrate and a first epitaxial layer adjacent to the first gate structure, in which a top surface of the first epitaxial layer includes a first V-shape. The LV device includes a second gate structure on the substrate and a second epitaxial layer adjacent to the second gate structure, in which a top surface of the second epitaxial layer includes a first planar surface.


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